on signal processing implementation on a DSP board

In this report, the DSP, and in general, digital and reconfigurable implementation of selected signal processing algorithms is described and analyzed in properly set up test beds. These laboratory prototypes allows to test the behavior of the signal processing algorithms when they are implemented on hardware platforms (DSPs and FPGAs), in the presence of data and metrics quantization, limited memory space and upper-bounded computational delay. A set of implementation solutions, designed to cope with the trade-off between hardware constraints and algorithm performance, has been presented, along with analysis of the results obtained from the laboratory test beds. The report presents the implementation of the basic mo-demodulation schemes of the IEEE 802.16 SC standard, on DSP and FPGA, along with a digital timing recovery scheme that allows the baseband receiver to work with just 2 samples/symbol with good performance. The performance of an ACM scheme implemented on a DSP board have been tested in an ad-hoc developed propagation channel model. Finally, computationally efficient encoding and decoding algorithms for iterative channel codes have been developed and successfully tested on a C-language directly suitable for DSP programming. Deliverable D18 CAP-D18-WP23-POL-PUB-03 This way, the practical and efficient feasibility of the main signal processing approaches previously presented in Deliverable D15 has been assessed in this report, by showing a number of possible solutions for implementing those algorithms on hardware supports, as well as drawing the guidelines to implement a fully integrated baseband Capanina transceiver. Keyword list: Signal Processing, Modulation and Coding, LDPC codes, LDPC encoders, Convolutional encoders, Soft-based iterative decoders, Reconfigurable Hardware, Hardware/Software Co-design, DSP, FPGA 31/05/06 FP6-IST-2003-506745-CAPANINA Page 2 of 99 Deliverable D18 CAP-D18-WP23-POL-PUB-03